1. Field of the Invention
The present invention relates in general to non-volatile memories. In particular, the present invention relates to implementing isolation for memory cells of non-volatile memory devices. More particularly, the present invention relates to a method for fabricating memory cells of non-volatile memory devices with improved isolation characteristics at restricted device dimensioning.
2. Technical Background
Memory cells within a semiconductor integrated circuit mass memory array require appropriate isolation between neighboring cells of the array. FIGS. 1-3 of the accompanying drawings show a typical prior art non-volatile memory device having multiple memory cells in the mass memory array.
In the conventional non-volatile memory device such as the one shown in plan view in FIG. 1, semiconductor substrate 1, typically a silicon substrate, is the basis for fabrication of arrays of non-volatile memory cells. As is realized by persons skilled in this art, the memory cells of the typical non-volatile memory device comprise field oxide 10, tunnel oxide 12, floating gate 14, gate dielectric 16, drain region 20, source region 22, word lines 18, and via 24 for electrical connecting to bit lines (not shown) of the memory device.
The structural configuration of such memory cells, as shown in the cross-sectional view of FIGS. 2 and 3 taken along the II--II and III--III lines in FIG. 1 respectively, however, is subjected to the disadvantageous effect of parasitic transistors that are established under field oxide 10. A conventional non-volatile memory cell employs P-type semiconductor substrate 1 to fabricate field oxide layer 10 on top of the substrate. The surrounding N.sup.+ -type regions 20, together with portions of the P-type semiconductor substrate 1 underneath the layer of field oxide 10 constitute N-channel parasitic transistors. Whenever a high voltage is applied to the interconnect (not shown) over the region of field oxide 10, the surrounding N.sup.+ -type regions 20 enter a conducting state and block the normal operation of the nearby non-volatile memory cells. Moreover, during the process of memory cell programming or erasing, N.sup.+ -type regions 20 are subjected to excessive electric potential sufficient to cause punchthrough in the parasitic transistors, further obscuring the normal operation of the memory cells of the non-volatile memory device.
Two solutions to the above-described problems of the disadvantageous effects caused by the inherent parasitic transistors within the memory device structural configuration were proposed in the prior art.
One solution employed field oxide layer 10 having increased thickness, for the purpose of increasing the threshold voltage of the inevitable parasitic transistor. The increase in the thickness of the field oxide layer, however, also results in the expansion of the bird's-beak of field oxide layer 10 into the active regions (namely, N.sup.+ -type region 20). This works against the effort of reducing the size of the memory device. Also, a thicker field oxide layer makes the surface contour of the integrated circuit device exhibit a greater gradient, which makes fabrication processing steps, such as step coverage and etching, more difficult to implement.
The other solution employed increased impurity concentration in the P-type semiconductor substrate in regions under field oxide layers 10 of the memory cells. The increased impurity concentration directly results in the increased threshold and punchthrough voltages of the inherent parasitic transistors. However, the disadvantageous side effect of this strategy is a reduction in the breakdown voltage between the N.sup.+ -type junction area and the P-type substrate.